/*This file is created by PINMAP tool
 *Device: //QogirN6Pro_UMS9620T
 *Version: UMS9620T_2_IRD_A_SCH_V1.0.0_PINMAP_V1.0
 *Create Time: 2022/01/18 14:16:20
 *Author: fei.pan
 */

#include <lk/reg.h>
#include <asm/arch/pinmap.h>
#include <power/sprd_pmic/sprd_9620_pinmap.h>
#include <power/sprd_pmic/sprd_9621_pinmap.h>
#include <power/sprd_pmic/sprd_9622_pinmap.h>

#define BIT_PIN_SLP_ALL		(BIT_PIN_SLP_AP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_ISE|BIT_PIN_SLP_CM4)
#define BIT_PIN_SLP_ALL_CP	(BIT_PIN_SLP_PSCP|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_AUDCP)
#define BIT_PIN_SLP_ALL_NO_CM4	(BIT_PIN_SLP_AP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_ISE)

static pinmap_t pinmap[]={
{REG_PIN_CTRL_REG0,0x00000000},//SIMCARD0_BAT_DET_AP
{REG_PIN_CTRL_REG1,0x00000000},//
//{REG_PIN_CTRL_REG2,0x00000000},//
{REG_PIN_CTRL_REG3,0x00000000},//
{REG_PIN_CTRL_REG4,0x00000000},//
{REG_PIN_CTRL_REG5,0x00100210},//WDRST_OUT_SEL->AP_WATCH_DOG;aon_usb_audio_iis->audcp vbc iis2 path;

//{REG_PIN_PWR_PAD_CTL_RESERVED,0x00000000},//
{REG_PIN_SIM_MATRIX_MTX_CFG,0x00000002},//SIM0->PSCP_SIM0;SIM1->PSCP_SIM1;
{REG_PIN_DMIC_MATRIX_MTX_CFG,0x00000000},//DMIC0->AUDCP_AUD_DMIC0;DMIC1->AUDCP_AUD_DMIC1;DMIC2->AUDCP_PDM_DMIC2
{REG_PIN_UART_MATRIX_MTX_CFG,0x5B970814},//UART0->PSCP_UART0;UART1->AP_UART1;UART2->AP_UART2;UART3->PHYCP_WCI2;UART4->CM4_UART0;UART5->CM4_UART2;UART6->PSCP_UART1;
{REG_PIN_UART_MATRIX_MTX_CFG1,0x00000086},//UART7->PHYCP_UART0;UART8->AUDDSP_UART0;
{REG_PIN_IIS_MATRIX_MTX_CFG,0x02904080},//IIS0->AP_IIS0;IIS1->AP_IIS1;IIS2->AP_IIS2;IIS3->AUDCP_IIS0;IIS4->AUDCP_IIS1;
{REG_PIN_IIS_MATRIX_MTX_CFG1,0x00000006},//IIS5->AUDCP_IIS2;IIS6->vbc_IIS2;
{REG_PIN_SPI_MATRIX_MTX_CFG,0x00000040},//SPI0->AP_SPI0;SPI1->AP_SPI1;SPI2->AP_SPI2;SPI3->CM4_SPI0;
{REG_PIN_IIC_MATRIX_MTX_CFG,0x76D23C10},//IIC0->AP_IIC0;IIC1->AP_IIC1;IIC2->CM4_I2C0;IIC3->AP_IIC3;IIC4->AP_IIC2;IIC5->CM4_I2C1;IIC6->AP_IIC6;IIC7->AP_IIC7
{REG_PIN_IIC_MATRIX_MTX_CFG1,0x0000054},//IIC8->AP_IIC4;IIC9->AP_IIC5
{REG_PIN_HOT_PLUG_DET_MATRIX_MTX_CFG,0x00000000},//HOTPLUG0->SIM0;HOTPLUG1->SIM1;HOTPLUG2->AP_SDIO0

//REG_PIN_xx    Function select
//REG_MISC_xx   Driver Strength | Strong pull up | Weak pull up/down | Sleep with subsystem | Weak pull up/down for sleep | Input/Output/Hi-Z for slp | SE
{REG_PIN_EMMC_RST,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_RST,                 BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//EMMC_RST
{REG_PIN_EMMC_CMD,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_CMD,                 BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//EMMC_CMD
{REG_PIN_EMMC_D0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D0,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D0
{REG_PIN_EMMC_D3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D3,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D3
{REG_PIN_EMMC_D2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D2,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D2
{REG_PIN_EMMC_D5,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D5,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D5
{REG_PIN_EMMC_CLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_CLK,                 BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//EMMC_CLK
{REG_PIN_EMMC_DS,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_DS,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_RCLK
{REG_PIN_EMMC_D1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D1,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D1
{REG_PIN_EMMC_D4,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D4,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D4
{REG_PIN_EMMC_D6,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D6,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D6
{REG_PIN_EMMC_D7,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_EMMC_D7,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//EMMC_D7
{REG_PIN_USB30_SW,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_USB30_SW,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//USB30_SW
{REG_PIN_DNS_D0,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_DNS_D0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//DNS_D0
{REG_PIN_DNS_D1,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_DNS_D1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AUDCP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//DNS_D1
{REG_PIN_LCM0_RSTN,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_LCM0_RSTN,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//LCM_RSTN
{REG_PIN_DSI0_TE,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_DSI0_TE,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//LCM_FMARK
{REG_PIN_PWMA,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_PWMA,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//LCM_BL_PWM
{REG_PIN_EXTINT0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//CTP_INT
{REG_PIN_EXTINT1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CTP_RST
{REG_PIN_SDA3,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA3,                     BITS_PIN_DS(3)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//NC
{REG_PIN_SCL3,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL3,                     BITS_PIN_DS(3)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//NC
{REG_PIN_DCDC_ARM1_EN,                  BITS_PIN_AF(0)},
{REG_MISC_PIN_DCDC_ARM1_EN,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCPU1_EN
{REG_PIN_PTEST,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_PTEST,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//GND
{REG_PIN_EXT_RST_B,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_EXT_RST_B,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//EXT_RST_B
{REG_PIN_ADI_SCLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ADI_SCLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ADI_SCLK
{REG_PIN_CLK_32K,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CLK_32K,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//CLK_32K
{REG_PIN_ANA_INT0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ANA_INT0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//ANA_INT0
{REG_PIN_ANA_INT1,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ANA_INT1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ANA_INT1(NC)
{REG_PIN_ANA_INT2,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_ANA_INT2,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ANA_INT2(NC)
{REG_PIN_ADI_D,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_ADI_D,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//ADI_D
{REG_PIN_AUD_SCLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_SCLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_SCLK
{REG_PIN_DCDC_ARM0_EN,                  BITS_PIN_AF(0)},
{REG_MISC_PIN_DCDC_ARM0_EN,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCPU0_EN
{REG_PIN_DCDC_ARM2_EN,                  BITS_PIN_AF(0)},
{REG_MISC_PIN_DCDC_ARM2_EN,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCPU2_EN
{REG_PIN_AUD_ADD0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_ADD0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AUD_ADD0
{REG_PIN_AUD_ADD1,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_ADD1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//AUD_ADD1
{REG_PIN_XTL_EN0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_XTL_EN0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EXT_XTL_EN0
{REG_PIN_AUD_ADSYNC,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_ADSYNC,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//AUD_ADSYNC
{REG_PIN_AUD_DAD0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DAD0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DAD0
{REG_PIN_XTL_EN1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_XTL_EN1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EXT_XTL_EN1
{REG_PIN_XTL_EN2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_XTL_EN2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//EXT_XTL_EN2
{REG_PIN_AUD_DASYNC,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DASYNC,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DASYNC
{REG_PIN_AUD_DAD1,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_AUD_DAD1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//AUD_DAD1
{REG_PIN_CHIP_SLEEP,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_CHIP_SLEEP,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CHIP_SLEEP
{REG_PIN_CHG_TYPE,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_CHG_TYPE,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//CHG_TYPE
{REG_PIN_SIM_DET0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SIM_DET0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//SIM_DET0
{REG_PIN_SIM_DET1,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SIM_DET1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//SIM_DET1
{REG_PIN_TF_DET,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_TF_DET,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//TF_DET
{REG_PIN_BAT_DET,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_BAT_DET,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BAT_DET
{REG_PIN_SCL4,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL4,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},// XJT, I2C
{REG_PIN_SDA4,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA4,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},// XJT, I2C
{REG_PIN_CLK_AUX1,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_CLK_AUX1,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//CLK_AUX1
{REG_PIN_IIS1DI,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//FTID_INT
{REG_PIN_IIS1DO,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//FTID_RSTN
{REG_PIN_IIS1CLK,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_IE},//CAMERA_FLASH_EN
{REG_PIN_IIS1LRCK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS1LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//camera_torch_en
{REG_PIN_SIMCLK0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SIMCLK0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//SIM0_CLK
{REG_PIN_SIMDA0,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SIMDA0,                   BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//SIM0_DA
{REG_PIN_SIMRST0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SIMRST0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//SIM0_RST
{REG_PIN_SIMCLK1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SIMCLK1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//SIM1_CLK
{REG_PIN_SIMDA1,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SIMDA1,                   BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_NUL|BIT_PIN_SLP_NONE|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//SIM1_DA
{REG_PIN_SIMRST1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SIMRST1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//SIM1_RST
{REG_PIN_SD0_CMD,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_CMD,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_CMD
{REG_PIN_SD0_D_0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_0,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D0
{REG_PIN_SD0_D_1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_1,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D1
{REG_PIN_SD0_CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_CLK,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_CLK0
{REG_PIN_SD0_D_2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_2,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D2
{REG_PIN_SD0_D_3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD0_D_3,                  BITS_PIN_DS(7)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//TF_SD0_D3
{REG_PIN_SD2_CMD,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_CMD,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_CMD
{REG_PIN_SD2_D0,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D0,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_D0
{REG_PIN_SD2_D1,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D1,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_D1
{REG_PIN_SD2_CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_CLK,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_CLK
{REG_PIN_SD2_D2,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D2,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_D2
{REG_PIN_SD2_D3,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_SD2_D3,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//WF_SD2_D3
{REG_PIN_IIS3DI,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS3DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//LCM_SOURCE_AVEEEN
{REG_PIN_IIS3DO,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS3DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//LCM_SOURCE_AVDDEN
{REG_PIN_IIS3LRCK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS3LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//BQ25970_INTacticelow
{REG_PIN_IIS3CLK,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS3CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//TOF_XSHUT
{REG_PIN_CLK_AUX2,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_CLK_AUX2,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//CLK_AUX2
{REG_PIN_RFCTL_0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_0
{REG_PIN_RFCTL_1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_1
{REG_PIN_RFCTL_2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_2
{REG_PIN_RFCTL_3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_3,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_3
{REG_PIN_RFCTL_4,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_4,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_4
{REG_PIN_RFCTL_5,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_5,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_5
{REG_PIN_RFCTL_6,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_6,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NR_5G_COEXIST
{REG_PIN_RFCTL_7,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_7,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_7
{REG_PIN_RFCTL_8,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_8,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//RFCTL_8
{REG_PIN_RFCTL_9,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_9,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//VDDCAMMOT_EN, XJT MODIFY
{REG_PIN_RFCTL_10,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_10,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCAMA1_EN
{REG_PIN_RFCTL_11,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_11,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCAMA0_EN
{REG_PIN_RFCTL_12,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_RFCTL_12,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//VDDCAMCORE_EN
{REG_PIN_RFCTL_13,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_RFCTL_13,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//GNSS_COEXIST
{REG_PIN_RFCTL_14,                      BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_14,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WB_WCI_2_RXD
{REG_PIN_RFCTL_15,                      BITS_PIN_AF(1)},
{REG_MISC_PIN_RFCTL_15,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//WB_WCI_2_RXD
{REG_PIN_RFFE0_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE0_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SCK0
{REG_PIN_RFFE0_SDA,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE0_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SDA0
{REG_PIN_RFFE1_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE1_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SCK1
{REG_PIN_RFFE1_SDA,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE1_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SDA1
{REG_PIN_RFFE2_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE2_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SCK2
{REG_PIN_RFFE2_SDA,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE2_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SDA2
{REG_PIN_RFFE3_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE3_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SCK3
{REG_PIN_RFFE3_SDA,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE3_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SDA3
{REG_PIN_RFFE4_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE4_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SCK4
{REG_PIN_RFFE4_SDA,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFFE4_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_ALL_CP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFFE_SDA4
{REG_PIN_RFFE5_SCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE5_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE5_SDA,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE5_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE6_SCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE6_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE6_SDA,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE6_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE7_SCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE7_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_RFFE7_SDA,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_RFFE7_SDA,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_LVDSRF_ADDAC0_ON,              BITS_PIN_AF(0)},
{REG_MISC_PIN_LVDSRF_ADDAC0_ON,         BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//LVDSRF_ADDAC0_ON
{REG_PIN_LVDSRF_ADDAC1_ON,              BITS_PIN_AF(0)},
{REG_MISC_PIN_LVDSRF_ADDAC1_ON,         BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//LVDSRF_ADDAC1_ON
{REG_PIN_LVDSRF_ADDAC2_ON,              BITS_PIN_AF(0)},
{REG_MISC_PIN_LVDSRF_ADDAC2_ON,         BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//LVDSRF_ADDAC2_ON
{REG_PIN_LVDSRF_ADDAC3_ON,              BITS_PIN_AF(0)},
{REG_MISC_PIN_LVDSRF_ADDAC3_ON,         BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//LVDSRF_ADDAC3_ON
{REG_PIN_RFSPI_SDA0,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SDA0,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSDA0
{REG_PIN_RFSPI_SDA1,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SDA1,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSDA1
{REG_PIN_RFSPI_SDA2,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SDA2,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSDA2
{REG_PIN_RFSPI_SDA3,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SDA3,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSDA3
{REG_PIN_RFSPI_SCK,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSCK
{REG_PIN_RFSPI_SEN,                     BITS_PIN_AF(0)},
{REG_MISC_PIN_RFSPI_SEN,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_PHYCP|BIT_PIN_SLP_PSCP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//RFSEN
{REG_PIN_SCL6,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL6,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C6_SCL
{REG_PIN_SDA6,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA6,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C6_SDA
{REG_PIN_VDSP_TDO,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_VDSP_TDO,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_VDSP_TDI,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_VDSP_TDI,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_VDSP_TMS,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_VDSP_TMS,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//BOARD_ID0
{REG_PIN_VDSP_TCK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_VDSP_TCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//BOARD_ID1
{REG_PIN_VDSP_RTCK,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_VDSP_RTCK,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_Z},//BOARD_ID2
{REG_PIN_DMIC_CLK2,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_CLK2,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//PDM_CLK2
{REG_PIN_DMIC_DATA2,                    BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_DATA2,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//PDM_DATA2
{REG_PIN_DMIC_CLK0,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_CLK0,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//CHG_INT
{REG_PIN_DMIC_DATA0,                    BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_DATA0,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//NC
{REG_PIN_DMIC_CLK1,                     BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_CLK1,                BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//CHG_EN_N
{REG_PIN_DMIC_DATA1,                    BITS_PIN_AF(3)},
{REG_MISC_PIN_DMIC_DATA1,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CHG_FLAG_N
{REG_PIN_U2TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U2TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BB_U2TXD
{REG_PIN_U2RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U2RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BB_U2RXD
{REG_PIN_U1TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U1TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BB_U1TXD
{REG_PIN_U1RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U1RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BB_U1RXD
{REG_PIN_U7TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BB_U7TXD
{REG_PIN_U7RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U7RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BB_U7RXD
{REG_PIN_U6TXD,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_U6TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//BB_U6TXD
{REG_PIN_U6RXD,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_U6RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//BB_U6RXD
{REG_PIN_MTCK_ARM,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_MTCK_ARM,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//MTCK
{REG_PIN_MTMS_ARM,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_MTMS_ARM,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_NONE|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//MTMS
{REG_PIN_AUD_DSP_TDO,                   BITS_PIN_AF(3)},
{REG_MISC_PIN_AUD_DSP_TDO,              BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_AUD_DSP_RTCK,                  BITS_PIN_AF(3)},
{REG_MISC_PIN_AUD_DSP_RTCK,             BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_AUD_DSP_TDI,                   BITS_PIN_AF(3)},
{REG_MISC_PIN_AUD_DSP_TDI,              BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_AUD_DSP_TCK,                   BITS_PIN_AF(3)},
{REG_MISC_PIN_AUD_DSP_TCK,              BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//TOF_GPIO
{REG_PIN_AUD_DSP_TMS,                   BITS_PIN_AF(3)},
{REG_MISC_PIN_AUD_DSP_TMS,              BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_CMMCLK0,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_MCLK0
{REG_PIN_CMMCLK1,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_MCLK1
{REG_PIN_CMMCLK2,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_MCLK2
{REG_PIN_CMMCLK3,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_CMMCLK3,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//NC
{REG_PIN_CMRST0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST0
{REG_PIN_CMRST1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST1
{REG_PIN_CMRST2,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST2,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST2
{REG_PIN_CMRST3,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST3,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST3
{REG_PIN_CMRST4,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST4,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_CMRST5,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_CMRST5,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_RST5
{REG_PIN_CMPD0,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD0,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN0
{REG_PIN_CMPD1,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD1,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN1
{REG_PIN_CMPD2,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD2,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN2
{REG_PIN_CMPD3,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD3,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_CMPD4,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD4,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NC
{REG_PIN_CMPD5,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_CMPD5,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//CAM_PWDN5
{REG_PIN_SCL0,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL0,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C0_SCL
{REG_PIN_SDA0,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA0,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C0_SDA
{REG_PIN_SCL1,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL1,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C1_SCL
{REG_PIN_SDA1,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA1,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C1_SDA
{REG_PIN_SCL8,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL8,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C8_SCL
{REG_PIN_SDA8,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA8,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C8_SDA
{REG_PIN_SCL9,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL9,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C9_SCL
{REG_PIN_SDA9,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_SDA9,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//I2C9_SDA
{REG_PIN_SPI3_CSN,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//CAMERA_FLASH_SYNC
{REG_PIN_SPI3_CLK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//COLOR_SENSOR_INT
{REG_PIN_SPI3_DI,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//EAR_CTL1
{REG_PIN_SPI3_DO,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI3_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//EAR_CTL2
{REG_PIN_SPI0_CSN,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//FTID_SPI_CS
{REG_PIN_SPI0_DO,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI0_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//FTID_SPI_DI
{REG_PIN_SPI0_DI,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI0_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//FTID_SPI_DO
{REG_PIN_SPI0_CLK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_SPI0_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//FTID_SPI_CLK
{REG_PIN_SCL2,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SCL2,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C2_SCL
{REG_PIN_SDA2,                          BITS_PIN_AF(0)},
{REG_MISC_PIN_SDA2,                     BITS_PIN_DS(1)|BIT_PIN_WPUS|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//I2C2_SDA
{REG_PIN_KEYOUT1,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYOUT1,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//PROX_INT
{REG_PIN_KEYOUT0,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYOUT0,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},// XJT: EVF_EN
{REG_PIN_KEYOUT2,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYOUT2,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//AG_INT1
{REG_PIN_EXTINT9,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT9,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//FS_EIS
{REG_PIN_EXTINT10,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_EXTINT10,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//WCHG_INT
{REG_PIN_KEYIN0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN0,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//KEYIN0
{REG_PIN_KEYIN1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN1,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//KETIN1
{REG_PIN_KEYIN2,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_KEYIN2,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//LCM_ID
{REG_PIN_SPI2_CSN,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_CSN,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//NC
{REG_PIN_SPI2_DO,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_DO,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//NC
{REG_PIN_SPI2_DI,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_DI,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//NC
{REG_PIN_SPI2_CLK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_SPI2_CLK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//NC
{REG_PIN_SD1_CMD,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_CMD,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//WF_SD1_CMD
{REG_PIN_SD1_D0,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D0,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//WF_SD1_D0
{REG_PIN_SD1_D1,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D1,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//WF_SD1_D1
{REG_PIN_SD1_CLK,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_CLK,                  BITS_PIN_DS(4)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//WF_SD1_CLK
{REG_PIN_SD1_D2,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D2,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//WF_SD1_D2
{REG_PIN_SD1_D3,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_SD1_D3,                   BITS_PIN_DS(3)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//WF_SD1_D3
{REG_PIN_U5TXD,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_U5TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_OE},//I2C5_SCL
{REG_PIN_U5RXD,                         BITS_PIN_AF(3)},
{REG_MISC_PIN_U5RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//I2C5_SDA
{REG_PIN_CLK_AUX0,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_CLK_AUX0,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WCN_32K_IN
{REG_PIN_U0TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BT_U0RXD
{REG_PIN_U0RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BT_U0TXD
{REG_PIN_U0CTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//BT_U0RTS
{REG_PIN_U0RTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U0RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_Z},//BT_U0CTS
{REG_PIN_IIS0DI,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//BT_PCM_OUT
{REG_PIN_IIS0DO,                        BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//BT_PCM_IN
{REG_PIN_IIS0CLK,                       BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//BT_PCM_CLK
{REG_PIN_IIS0LRCK,                      BITS_PIN_AF(0)},
{REG_MISC_PIN_IIS0LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//BT_PCM_SYNC
{REG_PIN_PWMC,                          BITS_PIN_AF(3)},
{REG_MISC_PIN_PWMC,                     BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_OE},//WF_HOST_WAKE
{REG_PIN_IIS4DO,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS4DO,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WB_CHIP_EN
{REG_PIN_IIS4DI,                        BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS4DI,                   BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_AP|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//WB_RST
{REG_PIN_IIS4CLK,                       BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS4CLK,                  BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//WB_INT
{REG_PIN_IIS4LRCK,                      BITS_PIN_AF(3)},
{REG_MISC_PIN_IIS4LRCK,                 BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_IE},//WF_WAKE_HOST
{REG_PIN_ESE_GPIO_N,                    BITS_PIN_AF(0)},
{REG_MISC_PIN_ESE_GPIO_N,               BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPD|BIT_PIN_SLP_AP|BIT_PIN_SLP_WPD|BIT_PIN_SLP_Z},//NFC_CLK_REQ
{REG_PIN_U4TXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4TXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//GPS_U1RXD
{REG_PIN_U4RXD,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4RXD,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//GPS_U1TXD
{REG_PIN_U4CTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4CTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_WPU|BIT_PIN_SLP_CM4|BIT_PIN_SLP_WPU|BIT_PIN_SLP_IE},//GPS_U1RTS
{REG_PIN_U4RTS,                         BITS_PIN_AF(0)},
{REG_MISC_PIN_U4RTS,                    BITS_PIN_DS(1)|BIT_PIN_NULL|BIT_PIN_NUL|BIT_PIN_SLP_CM4|BIT_PIN_SLP_NUL|BIT_PIN_SLP_OE},//GPS_U1CTS

};



static pinmap_t adie_pinmap[]={
/*here is the adie pinmap such as 9620*/
{REG_PIN_ANA_ADI_SCLK,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_ADI_D,             BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(3)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_PTESTO,            BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},//NC
{REG_PIN_ANA_EXT_RST_B,         BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_ANA_INT,           BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_CHIP_SLEEP,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_DCDC_CPU1_EN,      BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_DCDC_CPU2_EN,      BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_CLK_32K,           BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_EXT_XTL_EN0,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},//EXT_XTL_EN0
{REG_PIN_ANA_EXT_XTL_EN1,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},//EXT_XTL_EN1
{REG_PIN_ANA_EXT_XTL_EN2,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},//EXT_XTL_EN2
{REG_PIN_ANA_EXT_XTL_EN3,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},//WB_CLK_REQ
{REG_PIN_ANA_EXT_XTL_EN4,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_EXT_XTL_EN5,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_EXT_XTL_EN6,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_RSTN_O,            BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_OTP_1,             BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_USB_FLAG,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_BATDET_OK,         BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_DNS_D0,            BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_DNS_D1,            BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_AUD_ADD0,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_AUD_ADD1,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_AUD_ADSYNC,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_AUD_DAD0,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_AUD_DAD1,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_AUD_DASYNC,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_AUD_SCLK,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_EXT_RSTN_A,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_XTL_EN0_O,         BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_XTL_EN1_O,         BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
{REG_PIN_ANA_CHIP_SLEEP_O,      BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
};

static pinmap_t adie_pinmap_9621[]={
/*here is the adie pinmap such as 9621*/
{REG_PIN_ANA_ADI_SCLK_9621,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_ADI_D_9621,             BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(3)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_CHIP_SLEEP_9621,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_DCDC_CPU_EN_9621,       BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_EXT_XTL_EN_9621,        BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_RSTN_1_9621,            BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_OTP_O_9621,             BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_OE},
};

static pinmap_t adie_pinmap_9622[]={
/*here is the adie pinmap such as 9622*/
{REG_PIN_ANA_ADI_SCLK_9622,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_ADI_D_9622,             BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(3)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_TDIG_9622,              BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_Z},
{REG_PIN_ANA_TSEN_SEL_9622,          BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_CHIP_SLEEP_IN_9622,     BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_NUL|BIT_ANA_PIN_SLP_NUL|BIT_ANA_PIN_SLP_IE},
{REG_PIN_ANA_XTL_EN1_9622,           BITS_ANA_PIN_AF(0)|BITS_ANA_PIN_DS(1)|BIT_ANA_PIN_WPD|BIT_ANA_PIN_SLP_WPD|BIT_ANA_PIN_SLP_IE},
};

int  pin_init(void)
{
    int i;
    for (i = 0; i < sizeof(pinmap)/sizeof(pinmap[0]); i++) {
         __raw_writel(pinmap[i].val, CTL_PIN_BASE + pinmap[i].reg);
    }

    for (i = 0; i < sizeof(adie_pinmap)/sizeof(adie_pinmap[0]); i++) {
        sci_adi_raw_write(CTL_ANA_PIN_BASE + adie_pinmap[i].reg, adie_pinmap[i].val);
    }

    for (i = 0; i < sizeof(adie_pinmap_9621)/sizeof(adie_pinmap_9621[0]); i++) {
         sci_adi_raw_write(CTL_ANA_PIN_BASE_9621 + adie_pinmap_9621[i].reg, adie_pinmap_9621[i].val);
    }

    for (i = 0; i < sizeof(adie_pinmap_9622)/sizeof(adie_pinmap_9622[0]); i++) {
         sci_adi_raw_write(CTL_ANA_PIN_BASE_9622 + adie_pinmap_9622[i].reg, adie_pinmap_9622[i].val);
    }

    return 0;
}

